DCDC Converter

Характеристики

Грузоподъёмность

нет данных

Вылет

нет данных

Повторяемость позиционирования

нет данных

Масса

нет данных

Степень защиты

нет данных

Характеристики из источника

Строки приведены так, как их печатает производитель: без перевода, пересчёта и сравнения.

EN EN_UVLO_START EN

> 1.2 V

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The switching frequency is programmable from

300 kHz (to 1.5MHz and provides the capability of)

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Remote Sense Differential Amplifier

0.5 V (<RS+<2.555V, 4kOhm)

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PVin, Vin

-0.3V to 25 V

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ton (min)

0.5 V

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at 95% and 120% of VREF. PGood signal is asserted

1.3 ms (after Vsns voltage reaches 0.95*0.6V=0.57V)

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Vcc/

6.8 V (6.8V)

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than FCCM operation, where the switching frequency

5.5 V (<Vin<21V)

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+ E/A

0.6 V

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IR38060

33 h

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Thermal Resistance, Junction to Ambient (θJA) (Note 3)

14.3 °C (/W)

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slope according to the clock frequency applied on

21 V

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Junction to PCB Thermal Resistance ƟJ-PCB

2 °C (/W)

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The default reference voltage of the error amplifier is

0.5 V (for both digital and analog mode. The default)

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The Over current (OC) fault protection circuit also

20 ms

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Accuracy

0 °C (< Tj < 105°C -0.5 +0.5)

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Track_En to P1V8. Figure 15 shows the

> 1.2 V

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modes and the result of the comparison sets the Vp

0.5 V

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have their SCL and SDA lines internally pulled up to

3.3 V (. Therefore, although this design provides)

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ton (min) frequency

0.5 V

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Vin = PVin = 12V, VO =

1.2 V (, IO = 35A, Fs =)

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PIN DIAGRAM

5 mm (X 7mm POWER QFN)

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(digital) accuracy

4.5 V (<Vcc<5.5V, -30uA<)

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of operation also, a 100 kOhm resistor is connected

> 1.2 V

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Iout_dig Accuracy

4.5 V (<Vcc<5.5V, 5A < Iout +/-5 %)

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RS+, RS-, RSo, PGD, Enable, OCset

-0.3V to 8 V ((Note 1))

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Reference Voltage

1.25 V (<VFB<2.555V)

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Vref

0.6 V

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P1V8

0 V (comparator with default upper and lower thresholds)

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Imon ( analog) accuracy 00C to 1250C,

4.5 V (<Vcc<5.5V, 5A < Iout <1 +/-1.5 A)

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sensing the inductor current through the RDS(on) of the

1.5 V

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TYPICAL APPLICATION DIAGRAMS

1.5 V (<PVin<16V)

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DAC2 (Reference DAC) Track_En

0 V

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Sequencing

0.6 V

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PVin

1 V (Vcc)

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Thermal Resistance, Junction to Ambient (θJA) (Note 3)

14.7 °C (/W)

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VPG_low(lower)

0.4 V (< Vref < 1.2V)

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Tracking

0 V (up from RC/RD)

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Since the output capacitor has a major role in the

-40 dB (/Decade)

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used by OVP comparator to detect an output over 0

0.5 V

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control loop bandwidth, thus reducing the required

0.5 V (for both digital and analog mode. The default)

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IR38163

63 h

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programmed using PMBus commands Fault DAC

0.5 V

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disappears

21 V

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The output LC filter introduces a double pole,

40 dB (/decade gain slope above its corner resonant)

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Remote Sense Differential Amplifier

0.5 V (<RS+<2.555V, 4kΩ load)

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The switching frequency can be programmed between

12.5 % (of the switching period before the inductor)

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 Output Voltage Range

0.6 V

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Vcc

> 1.2 V

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PGND to GND, RS- to GND

-0.3 V (to + 0.3V)

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POWER_GOOD_ON and POWER_GOOD_OFF

0.4 V

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actual capacitance value and the Equivalent Series

0 dB (crossing frequency and adequate phase margin)

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(a) Vo2 (slave)

0 V

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Series Resistance (ESR). However the actual

0 dB (crossing frequency and adequate phase margin)

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VCC

-0.3V to 6 V

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400C<Tj<1250C VOUT_SCALE_LOOP=1;

0.45 V (<VFB<0.75V)

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switching frequencies be avoided

250 kHz (, 300 kHz,)

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IL

20 ms

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DAC2 (Reference DAC)

0 V

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_SS 0.15V

0.15 V

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PGND to LGND, RS- to LGND

-0.3V to +0.3 V

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make the on-time during diode emulation adaptive

3 V (, it is recommended to use local sensing, or if)

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Vcc

> 0.6 V

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Storage Temperature Range

-55°C to 150 °C

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VOUT_SCALE_LOOP=1;

0.45 V (<VFB<0.75V)

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Accuracy

4.5 V (<Vcc<5.5V, -30uA<)

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1.5 0 1.5 mV

0 °C (< Tj < 85°C)

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This transition is to gradually make the actual

250 kHz to 1500 kHz (. The user can override this using)

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> 1.2V DAC2 (Reference DAC)

1.2 V

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IR38062

32 h

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skipping, which can cause high inductor current ripple

0.5 V (for both digital and analog mode. The default)

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EN

> 1.2 V (Vd Bootstrap diode forward voltage. [0.8V])

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High state indicates that output is in regulation. It 0.4V

0.3 V

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problems. Stencils in the range of 0.125mm

0.200 mm ((0.005-0.008”), with suitable)

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Output Voltage Range

0.5 V

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following switching frequencies be avoided

250 kHz (, 300 kHz, 400 kHz, 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1)

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auto-restart when over temperature condition

16 V

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Vsns

0.45 V

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traces should be at least 0.05mm larger (on

0.05 mm (in X & Y), in order to accommodate)

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IR3448

21 V

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High state indicates that output is in regulation. It

0.4 V

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initialization sequence is complete, the ADC no

813 kHz (, 978 kHz, 1171 kHz and 1454 kHz)

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> 1.2V > 1.2V

1.2 V (EN)

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(JESD22-A115A)

<200 V

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Figure 2

IR38263 Package Top View: 5 mm (X 7mm PQFN)

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Damage is not expected when PGood is back biased,

0 V

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VDDQ

12.5 % (until it reaches the steady state value. The)

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> 1.2V

> 1.2 V

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VOUT_OV_WARN_LIMIT,VOUT_UV_FAULT_LIMIT Vsns

0.45 V

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The switching frequency is programmable from

300 kHz (to 1.5MHz and provides the capability of ENABLE)

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2 2 mV

-40 °C (< Tj < 125°C)

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Vo1 (master) Tracking

0 V (up from =RC/RD)

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[V] Vo

0.15 V

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P1V8

0 V

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Thermal Resistance, Junction to Case (θJC_TOP)

30 °C (/W)

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frequency. Figure 18 shows the LDO voltage for

600 kHz (and 1000kHz switching frequency.)

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than FCCM operation, where the switching

5.5 V (<Vin<16V)

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current sense resistor and any layout related noise

0.15 V

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BOOT

-0.3V to 33 V

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Vo1 (master) Tracking 0V up from =RC/RD

0 V

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Reference DAC

0.5 V

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Cbyp

0.6 V

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Thermal Resistance, Junction to Case Top (θJC_TOP)

31.5 °C (/W)

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extended operating bus voltage (PVin) range from

1.2V to 16 V (.)

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VCC, Enable

-0.3V to 8 V ((Note 1))

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Input/Output pins

-0.3V to 3.9 V

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Sets the value of the output current, in

40 A (,)

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Power good detection and output overvoltage Reference DAC

0.5 V

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Vcc

0 V

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Figure 47

0.35 V

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Figure 2

IR38163/363/165/365 Package Top View: 5 mm (X 7mm PQFN)

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ensure operation with a pulse width that is higher

0.5 V (for both digital and analog mode. The default)

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EN

> 1.2 V

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PVin

1 V

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detection rely on fast analog comparator circuits, Fault DAC

0.5 V

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(b) Vo2 (slave)

0 V

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IR38061

31 h

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DCDC Converter

35 A (Highly Integrated SupIRBuck®)

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and VOUT_UV_WARN_LIMIT respectively. Reference DAC

0.5 V

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t on (min)

0.6 V

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Iout_dig Accuracy 00C to 1250C,

4.5 V (<Vcc<5.5V, 5A < Iout <3 +/-5 %)

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The output starts in asynchronous fashion and keeps

0ms to 127 ms (, and the resolution is 1 ms. Further,)

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EN

> 1.2 V (PB)

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Vref

0 V

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Iout_dig Accuracy 00C to 1250C,

4.5 V (<Vcc<5.5V, 5A < Iout <2 +/-5 %)

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IR38263

65 h

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BASIC APPLICATION

5.5 V (<PVin<16V)

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PVin=Vin

12.5 % (25% ... 87.5%)

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Input Offset Voltage

0.6 V (Vref)

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overall performance of the converter and determines

-40 dB (/Decade)

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Vcc

> 1.2 V (Vp)

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Accuracy

1.25 V (<VFB<2.555V %)

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In general, AOT operation is more jittery and noisier

5.5 V (<Vin<21V)

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P1V8

-0.3V to 2 V

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ΔV0 = Output Voltage Ripple

-40 dB (/Decade)

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The switching frequency can be programmed between

300kHz – 1500 kHz (by connecting an external resistor)

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IL Tblk_Hiccup

20 ms

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disappears

12 V (12V)

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BOOT to SW

-0.3V to 6 V ((DC) (Note 1), -0.3V to 6.5V (AC, 100ns))

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Power Good Low Upper

0.4 V (< Vref < 1.2V)

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voltage to the corresponding thresholds

> 1.2 V

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Thermal Resistance, Junction to Case Top (θJC_TOP)

32 °C (/W)

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VCC

-0.3V to 8 V ((Note 1))

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Where

0 dB (00)

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Vp

> 1.0 V (Enable used as logic input. For this mode of)

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Mode

1.2 V ((Slave))

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Effective Series Resistance (ESR). However the

40 dB (/decade gain slope above its corner resonant)

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i2c/PMBus™ mode

5 A (< Iout <30A)

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Figure 2

IR38265 Package Top View: 5 mm (X 7mm PQFN)

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BASIC APPLICATION

5.5 V

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used by OVP comparator to detect an output over Vsns

0.45 V

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Junction Temperature Range

-40°C to 150 °C ((Note1))

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Accuracy

4.5 V (<Vcc<5.5V, -30uA< -9 9 °C)

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switching frequencies be avoided

250 kHz, 300 kHz,: 400 kHz (, 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1)

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The Over Current (OC) protection is performed by

3.0 V

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VOUT_SCALE_LOOP=1;

1.25 V (<VFB<2.555V %)

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BOOT

-0.3V to 31 V

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IR38064

34 h

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gradually. In order to minimize the impact from these

12 V (12V)

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DCDC Converter

25 A (Single-input Voltage, Synchronous OPTIMOS IPOL)

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Vin = PVin = 12V, VO =

1.2 V (, IO = 25A, Fs =)

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 Output Voltage Range

0.5 V (to 0.875*PVin)

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(Dyn)

600 kHz

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respectively. The bus voltage reading as reported by

> 1.2 V

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Enable (slave)

1.2 V

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PGD

0.6 V

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IR38060

30 h

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These components can be described as

0 dB (crossing frequency and adequate phase margin)

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Moisture Sensitivity Level

5mm x 7 mm (PQFN MSL3)

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PVin

-0.3V to 25 V

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the Vp pin of the slave exceeds 0.5V, the internal

0.5 V (reference of the slave dictates its output)

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Vin

-0.3V to 25 V

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DCDC Converter

35 A (Single-input Voltage, Synchronous Digital SupIRBuck)

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regulation window. In digital mode, this delay is 0

0.5 V

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Thermal Resistance, Junction to Ambient (θJA) (Note 3)

15.4 °C (/W)

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Junction Temperature Range

-40°C to 150 °C

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PIN DIAGRAM

5 mm (X 6mm POWER QFN)

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RS+, RS-, RSo, PGD, OCset

-0.3 V (to VCC + 0.3V (Note 2))

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BOOT to SW

-0.3V to 6 V ((DC), -0.3V to 6.5V (AC, 100ns))

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> 0.6V

0.6 V

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BASIC APPLICATION

5.5 V (<Vin<21V)

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PGD, other Input/output pins

-0.3V to 6 V ((Note 1))

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DCDC Converter

25 A (Highly Integrated SupIRBuck®)

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Iout_dig Accuracy 00C to 1250C,

4.5 V (<Vcc<5.5V, 5A < Iout <1 +/-5 %)

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switching frequencies be avoided

250 kHz (, 300 kHz, gradually.)

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Soft Start (slave)

0 V

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IR38063

33 h

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DCDC Converter

6 A (Single-input Voltage, Synchronous Digital SupIRBuck)

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Sets the value of the output current, in

35 A (, amperes, that causes the overcurrent detector to)

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Vo1 (master) P1V8

0 V

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Thermal Resistance, Junction to PCB (pin 29) (θJB)

2.98 °C (/W)

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VIN_OFF, VIN_OV_FAULT_LIMIT and

> 1.2 V

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Thermal Resistance, Junction to PCB (θJB)

2.41 °C (/W)

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Vp

> 1.2 V

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IR38365

68 h

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should be about 200mV greater than the

5.5 V (<Vin<16V)

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SW

-0.3V to 25 V ((DC), -4V to 25V (AC, 100ns))

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traces should be at least 0.05mm larger (on

0.05 mm (in X & Y), in order to accommodate any)

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Moisture Sensitivity Level

5mm x 7 mm (PQFN MSL 2 260C)

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POWER_GOOD_ON and POWER_GOOD_OFF 0.4V

0.3 V

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IR38363

67 h

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different operating modes. The Vsns signal is also

0.605 V

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Junction to Ambient Thermal Resistance ƟJA

30 °C (/W)

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Moisture Sensitivity Level

5mm x 6 mm (PQFN MSL2)

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Other Input/Output pins

-0.3V to 3.9 V

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Vcc EN

> 1.2 V (DAC2 (Reference DAC))

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PMBus command. In addition to the default

0.5 V

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SW

50 % (ripple of the output current. For the buck)

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P1V8

1.2 V (Non-tracking))

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Intl

0.65 V

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Tracking 0V up from RC/RD

0 V

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the output voltage (for output voltages lower than

2.555 V (, without any resistive divider on the Fb pin),)

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> 1.2V Vp

1.2 V

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Imon ( analog) accuracy 0 0C to 1250C,

4.5 V (<Vcc<5.5V, Iout=6A, -)

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Accuracy

0.75 V (<VFB<1.25V)

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recommended startup sequence for tracking

> 1.2 V

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Figure 27

Typical waveforms for sequencing: 0 V

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Rt/Sync pin. Even though the frequency of the

12 V (12V)

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LDO

4.4 V

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on the downward inductor current slope approximately

12.5 % (of the switching period before the inductor)

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BOOT to SW

-0.3 V (to VCC + 0.3V (Note 2))

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comparator window thresholds. The PGood pin is 0.4V

0.3 V

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voltage path. Fault DAC

0.5 V

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RS+, RS-, RSo, PGD, OCset, S_Ctrl

-0.3 V (to VCC + 0.3V (Note 2))

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Figure 14

Recommended startup for sequencing: 12 V

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Enable

1.2 V (1.0V results to lower closed loop bandwidth.)

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DCDC Converter

25 A (Single-input Voltage, Synchronous Digital SupIRBuck)

источник 7

Figure 5 shows the recommended startup sequence

12.5 % (25% ... 87.5%)

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severe load step-down transient causing OVP, the

0.6 V

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IR38065

35 h

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Vo = output voltage

0.6 V

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DCDC Converter

15 A (Single-input Voltage, Synchronous Digital SupIRBuck)

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tracking and/or sequencing options using Vp,

5.5 V (<Vin<21V)

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Iout_dig Accuracy 0 0C to 1250C,

4.5 V (<Vcc<5.5V, Iout=6A +/-5 %)

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operation (ratiometric or simultaneous)

12 V

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EN

> 1.2 V (Voltage)

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Power Good High Lower

0.4 V (< Vref < 1.2V)

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R3 C3

-40 dB (/Decade R5 Zf)

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mode of operation

(a) simultaneous, (b): 0 V

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operation of IR38060 with Enable used as logic

> 1.2 V

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PVin

6.8 V

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Figure 47

0.4 V

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PVin

5 V

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TYPICAL APPLICATION DIAGRAMS

5.5 V (<Vin<16V)

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DCDC Converter

16 A (Highly Integrated SupIRBuck®)

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comparator window thresholds. The PGood pin is

0.4 V

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Figure 27

Typical waveforms for sequencing Tracking: 0 V (up from =RC/RD)

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DDR/Vtt rail applications). The effective Vp range is

0V~1.2 V (.)

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EN EN_UVLO_START

0 V

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Moisture Sensitivity Level

5mm x 6 mm (PQFN MSL 2 260C)

источник 4

and enhance minimum pulse width which utilizes the

0.15 V

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Thermal Resistance, Junction to PCB (θJB)

2.71 °C (/W)

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IL

20 ms (every sequence of 4 consecutive cycles in which the)

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extended operating bus voltage (PVin) range from

1.2V to 21 V (.)

источник 7

undervoltage faults and warnings rely on comparing Vsns

0.45 V

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by the PMBus commands VIN_ON, VIN_OFF,

> 1.2 V

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EN EN_UVLO_START DAC2 (Reference DAC)

0 V

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Ideally, the input with the lowest voltage is used for

5.5 V (<Vin<21V)

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IR3447 can also use an external bias to provide gate

600 kHz (and 1000kHz switching frequency.)

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Vin pin, and an external Vcc supply between 4.5V and

5.5 V (may be used, allowing an extended operating)

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Vout reporting accuracy 00C to 850C, 4.5V<Vcc<5.5V,

1 V (<Vsns≤ 1.5V +/-0.6)

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operation (ratiometric or simultaneous)

10.2 V

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output capacitor’s ESR generates a zero at 5kHz to

50 kHz

источник 7

Источники

1. DCDC Converter

   страница товара; от производителя; издатель: Infineon; редакция: 2026-10-02

   Где в источнике: EN EN_UVLO_START EN; ton (min); The default reference voltage of the error amplifier is; modes and the result of the comparison sets the Vp; have their SCL and SDA lines internally pulled up to; of operation also, a 100 kOhm resistor is connected; P1V8; Since the output capacitor has a major role in the; (a) Vo2 (slave); Series Resistance (ESR). However the actual; switching frequencies be avoided; DAC2 (Reference DAC); make the on-time during diode emulation adaptive; IR38062; Figure 47; Vcc; In general, AOT operation is more jittery and noisier; used by OVP comparator to detect an output over Vsns; switching frequencies be avoided: 250 kHz, 300 kHz,; respectively. The bus voltage reading as reported by; Iout_dig Accuracy 00C to 1250C,; Soft Start (slave); different operating modes. The Vsns signal is also; > 1.2V Vp; comparator window thresholds. The PGood pin is 0.4V; DCDC Converter; tracking and/or sequencing options using Vp,; comparator window thresholds. The PGood pin is; Vin pin, and an external Vcc supply between 4.5V and; operation (ratiometric or simultaneous)

2. DCDC Converter

   технический лист; от производителя; издатель: Infineon; редакция: 2026-10-02

   Где в источнике: The switching frequency is programmable from; at 95% and 120% of VREF. PGood signal is asserted; Thermal Resistance, Junction to Ambient (θJA) (Note 3); Vin = PVin = 12V, VO =; PIN DIAGRAM; Vref; Sequencing; VPG_low(lower); Tracking; The output LC filter introduces a double pole, -;  Output Voltage Range; _SS 0.15V; PGND to LGND, RS- to LGND; Storage Temperature Range; -1.5 0 1.5 mV; EN; (JESD22-A115A); Damage is not expected when PGood is back biased,; VDDQ; -2 2 mV; Thermal Resistance, Junction to Case (θJC_TOP); BOOT; VCC, Enable; DCDC Converter; t on (min); Input Offset Voltage; ΔV0 = Output Voltage Ripple; Power Good Low Upper; Where; Vp; Junction Temperature Range; Moisture Sensitivity Level; PVin; Vin; SW; traces should be at least 0.05mm larger (on; Other Input/Output pins; Intl; Tracking 0V up from RC/RD; on the downward inductor current slope approximately; BOOT to SW; RS+, RS-, RSo, PGD, OCset, S_Ctrl; Enable; Power Good High Lower; DDR/Vtt rail applications). The effective Vp range is; and enhance minimum pulse width which utilizes the; Thermal Resistance, Junction to PCB (θJB)

3. DCDC Converter

   страница товара; от производителя; издатель: Infineon; редакция: 2026-10-03

   Где в источнике: Remote Sense Differential Amplifier; than FCCM operation, where the switching frequency; IR38060; Imon ( analog) accuracy 00C to 1250C,; PVin; programmed using PMBus commands Fault DAC; Vcc; This transition is to gradually make the actual; skipping, which can cause high inductor current ripple; auto-restart when over temperature condition; (b) Vo2 (slave); IR38061; and VOUT_UV_WARN_LIMIT respectively. Reference DAC; Iout_dig Accuracy 00C to 1250C,; The output starts in asynchronous fashion and keeps; disappears; DCDC Converter; regulation window. In digital mode, this delay is 0; switching frequencies be avoided; SW; P1V8; the output voltage (for output voltages lower than; recommended startup sequence for tracking; Figure 27: Typical waveforms for sequencing; IR38065; operation (ratiometric or simultaneous); by the PMBus commands VIN_ON, VIN_OFF,; EN EN_UVLO_START DAC2 (Reference DAC); Ideally, the input with the lowest voltage is used for

4. DCDC Converter

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   Где в источнике: PVin, Vin; Junction to PCB Thermal Resistance ƟJ-PCB; The Over current (OC) fault protection circuit also; ton (min) frequency; (digital) accuracy; Reference Voltage; control loop bandwidth, thus reducing the required; disappears; Remote Sense Differential Amplifier; PGND to GND, RS- to GND; VCC; VOUT_SCALE_LOOP=1;; > 1.2V DAC2 (Reference DAC); High state indicates that output is in regulation. It 0.4V; • Output Voltage Range; High state indicates that output is in regulation. It; initialization sequence is complete, the ADC no; Vo1 (master) Tracking; P1V8; than FCCM operation, where the switching; Vo1 (master) Tracking 0V up from =RC/RD; Reference DAC; extended operating bus voltage (PVin) range from; Power good detection and output overvoltage Reference DAC; PVin; BASIC APPLICATION; Accuracy; voltage to the corresponding thresholds; BOOT; IR38064; IR38060; These components can be described as; the Vp pin of the slave exceeds 0.5V, the internal; BOOT to SW; PGD, other Input/output pins; IR38063; DCDC Converter; Vo1 (master) P1V8; Vp; should be about 200mV greater than the; Junction to Ambient Thermal Resistance ƟJA; Vcc EN; PMBus command. In addition to the default; Imon ( analog) accuracy 0 0C to 1250C,; voltage path. Fault DAC; Iout_dig Accuracy 0 0C to 1250C,; R3 C3; operation of IR38060 with Enable used as logic; Figure 47; EN EN_UVLO_START; Moisture Sensitivity Level; undervoltage faults and warnings rely on comparing Vsns; Vout reporting accuracy 00C to 850C, 4.5V<Vcc<5.5V,

5. DCDC Converter

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   Где в источнике: Vcc/; + E/A; slope according to the clock frequency applied on; sensing the inductor current through the RDS(on) of the; Thermal Resistance, Junction to Ambient (θJA) (Note 3); The switching frequency can be programmed between; problems. Stencils in the range of 0.125mm-; traces should be at least 0.05mm larger (on; current sense resistor and any layout related noise; Cbyp; Thermal Resistance, Junction to Case Top (θJC_TOP); Effective Series Resistance (ESR). However the; The Over Current (OC) protection is performed by; Vin = PVin = 12V, VO =; Junction Temperature Range; PIN DIAGRAM; RS+, RS-, RSo, PGD, OCset; DCDC Converter; Thermal Resistance, Junction to PCB (θJB); Moisture Sensitivity Level; Rt/Sync pin. Even though the frequency of the; LDO; Figure 5 shows the recommended startup sequence; Vo = output voltage; EN; PVin; IR3447 can also use an external bias to provide gate

6. DCDC Converter

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   Где в источнике: Accuracy; RS+, RS-, RSo, PGD, Enable, OCset; IR3448; The switching frequency is programmable from; [V] Vo; frequency. Figure 18 shows the LDO voltage for; Input/Output pins; EN; PVin=Vin; The switching frequency can be programmed between; Thermal Resistance, Junction to Case Top (θJC_TOP); VCC; gradually. In order to minimize the impact from these; (Dyn); PGD; Thermal Resistance, Junction to Ambient (θJA) (Note 3); Thermal Resistance, Junction to PCB (pin 29) (θJB); severe load step-down transient causing OVP, the; DCDC Converter

7. DCDC Converter

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   Где в источнике: Track_En to P1V8. Figure 15 shows the; DAC2 (Reference DAC) Track_En; used by OVP comparator to detect an output over 0; POWER_GOOD_ON and POWER_GOOD_OFF; actual capacitance value and the Equivalent Series; Accuracy; Vsns; > 1.2V > 1.2V; > 1.2V; VOUT_OV_WARN_LIMIT,VOUT_UV_FAULT_LIMIT Vsns; Vcc; ensure operation with a pulse width that is higher; detection rely on fast analog comparator circuits, Fault DAC; Iout_dig Accuracy 00C to 1250C,; overall performance of the converter and determines; Mode; Enable (slave); BASIC APPLICATION; VIN_OFF, VIN_OV_FAULT_LIMIT and; POWER_GOOD_ON and POWER_GOOD_OFF 0.4V; Figure 14: Recommended startup for sequencing; DCDC Converter; mode of operation: (a) simultaneous, (b); Figure 27: Typical waveforms for sequencing Tracking; IL; extended operating bus voltage (PVin) range from; output capacitor’s ESR generates a zero at 5kHz to

8. DCDC Converter

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   Где в источнике: Iout_dig Accuracy; TYPICAL APPLICATION DIAGRAMS; -400C<Tj<1250C VOUT_SCALE_LOOP=1;; IL; Vcc; following switching frequencies be avoided; Figure 2: IR38263 Package Top View; IR38263; IL Tblk_Hiccup; BOOT to SW; VOUT_SCALE_LOOP=1;; > 0.6V; Moisture Sensitivity Level; PVin

9. DCDC Converter

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   Где в источнике: IR38163; Sets the value of the output current, in; Figure 2: IR38163/363/165/365 Package Top View; i2c/PMBus™ mode; DCDC Converter;  Output Voltage Range; IR38365; IR38363; TYPICAL APPLICATION DIAGRAMS

10. DCDC Converter

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    Где в источнике: Figure 2: IR38265 Package Top View; BASIC APPLICATION